The present invention relates to a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique for use in the fabrication of a semiconductor integrated circuit device, including an SRAM (Static Random Access Memory).
Cache memories of personal computers and workstations use an SRAM, the memory cells of which are each formed of six MISFETs (Metal Insulator Semiconductor Field Effect Transistors). More specifically, a memory cell is made up of a flip-flop circuit for storing 1-bit of data and two data transfer MISFETs, and the flip-flop circuit is formed of a pair of drive MISFETs and a pair of load MISFETs, for example.
Each MISFET has its source-drain regions overlaid with a silicide layer, which reduces the resistance of the source-drain regions and also reduces the contact resistance with plugs which are formed on the regions. The MISFET also has its gate electrode overlaid with a silicide layer, which reduces the resistance of the gate electrode.
The silicide layer is formed in a self-alignment manner (technique of salicide structure) by, for example, depositing a metallic film on the source-drain regions and gate electrode, and inducing the reaction of silicification in the contact section between the source-drain regions (silicon substrate) and the metallic film and in the contact section between the gate electrode (silicon layer) and the metallic film. Japanese Patent Unexamined Publication No. Hei 9(1997)-199720 describes a technique for forming a silicide layer on the source-drain regions and gate electrode.